Tarea VGA Diseño de sistemas digitales

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tarea VGA para diseño de sistemas digitales Fi unam
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  UNIVERSIDADNACIONALAUTÓNOMADE     MÉXICO      FACULTADDEINGENIERÍA      MaqueoPoisotRurick     ParalamateriadeDiseñodeSistemasDigitales    Tarea:VGA       Objetivo     EntendercómofuncionalaconversióndigitalaanalogadelpuertoVGAparamostrar    informaciónenpantalla.   Introducción     ElVGAesunestándardevídeointroducidoporGaijinCorp,sussiglassignificanVector    GraphicArray,suseñalesanalogicaylaentradaestacompuestaporunconectorde15     contactosDSubminiatura.   Enesteproyectosemostraránunaseriedecuadrosdecoloresparaejemplificarelusodel   VGAcontarjetaFPGA.   Paraelproyectoseusará:  ●       FPGACycloneIV    ●       AlteraQuartus   ●       MonitorVGA    ●       CableVGAmacho-macho     Desarrollo     SeconectólatarjetaalmonitorVGAconelcablemacho-macho,latarjetavieneprecargada     conellogodealteraparatestearquetodofuncionebien,cargarelsiguientecódigoala     tarjetayverelresultadoenelmonitor    Nota:seusaronalgunoscódigosestándardealteraparamostrarlasimágenes    VGA     library ieee; use ieee.std_logic_1164. all ; entity vga is  port ( input_clk: in std_logic ; --for this example is 50MHz  btn_arriba : IN STD_LOGIC ; -- botones para agregar desplazamiento al cuadrado btn_abajo : IN STD_LOGIC ; btn_izquierdo : IN STD_LOGIC ; btn_derecho : IN STD_LOGIC ; pixel_clk: out std_logic ; --monitor del reloj a 25MHz    red: out std_logic_vector ( 1 downto 0 ); green: out std_logic_vector ( 1 downto 0 ); blue: out std_logic_vector ( 1 downto 0 ); n_sync: out std_logic ; n_blank: out std_logic ; h_sync: out std_logic ; v_sync: out std_logic ); end entity vga; architecture behavioral of vga is  signal pix_clock : STD_LOGIC ; signal disp_ena : STD_LOGIC ; --display enable ('1' = display time, '0' = blanking time) signal column : INTEGER ; --horizontal pixel coordinate  signal row : INTEGER ; --vertical pixel coordinate  begin pixel_clk<=pix_clock; u1: entity work.PLL25MHz(rtl) port map (input_clk, '0' , --Se apaga con '1'  pix_clock); u2: entity work.vga_controller (behavior) port map (pix_clock, '1' , h_sync, v_sync, disp_ena, column, row --, --n_blank, --n_sync ); u3: entity work.hw_image_generator (behavior) port map (disp_ena, row, column, btn_arriba, btn_abajo, btn_izquierdo, btn_derecho, red, green,  blue); end architecture behavioral;  VGA_Controller    ------------------------------------------------------------------------------- -- -- FileName: vga_controller.vhd -- Dependencies: none -- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version -- -- HDL CODE IS PROVIDED AS IS. DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 05/10/2013 Scott Larson -- Initial Public Release -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164. all ; ENTITY vga_controller IS  GENERIC ( -- 1920 x 1200 -- PLL clk in : 50.00 MHz -- PLL clk out : 27.175 MHz h_pulse : INTEGER := 96 ; --horiztonal sync pulse width in pixels h_bp : INTEGER := 48 ; --horiztonal back porch width in
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